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1 features ? low-voltage and standard-voltage operation ? 2.7 (v cc = 2.7v to 5.5v) ? 1.8 (v cc = 1.8v to 5.5v) user selectable internal organization ? 16k: 2048 x 8 or 1024 x 16 3-wire serial interface sequential read operation schmitt trigger, filtered inputs for noise suppression 2 mhz clock rate (5v) compatibility self-timed write cycle (10 ms max) high reliability ? endurance: 1 million write cycles ? data retention: 100 years automotive grade, extended temperature and lead-free/halogen-free devices available 8-lead pdip, 8-lead jedec soic, 8-lead map and 8-lead tssop packages description the AT93C86A provides 16384 bits of serial electrically erasable programmable read only memory (eeprom) organized as 1024 words of 16 bits each when the org pin is connected to v cc and 2048 words of 8 bits each when it is tied to ground. the device is optimized for use in many industrial and commercial applications where low power and low voltage operations are essential. the AT93C86A is available in space saving 8-lead pdip, 8-lead jedec soic, 8-lead map and 8-lead tssop packages. 3-wire serial eeprom 16k (2048 x 8 or 1024 x 16) AT93C86A preliminary rev. 3408c?seepr?1/04 pin configurations pin name function cs chip select sk serial data clock di serial data input do serial data output gnd ground vcc power supply org internal organization dc don?t connect 8-lead pdip 1 2 3 4 8 7 6 5 cs sk di do vcc dc org gnd 8-lead soic 1 2 3 4 8 7 6 5 cs sk di do vcc dc org gnd 8-lead tssop 1 2 3 4 8 7 6 5 cs sk di do vcc dc org gnd 8-lead map bottom view 1 2 3 4 8 7 6 5 vcc dc org gnd cs sk di do
2 AT93C86A [preliminary] 3408c?seepr?1/04 the AT93C86A is enabled through the chip select pin (cs), and accessed via a 3-wire serial interface consisting of data input (di), data output (do), and shift clock (sk). upon receiving a read instruction at di, the address is decoded and the data is clocked out serially on the data output pin do. the write cycle is completely self- timed and no separate erase cycle is required before write. the write cycle is only enabled when the part is in the erase/write enable state. when cs is brought ?high? following the initiation of a writ e cycle, the do pin outputs the ready/busy status of the part. the AT93C86A is available in a 2.7v to 5.5v version. block diagram note: 1. when the org pin is connected to vcc, the x 16 organization is selected. when it is connected to ground, the x 8 organiz a- tion is selected. if the org pin is left unconnected and the application does not load the input beyond the capability of the internal 1 meg ohm pullup, then the x 16 organization is selected. this feature is not available on the 1.8v devices. absolute maximum ratings* operating temperature................................. -55 c to +125 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability storage temperature .................................... -65 c to +150 c voltage on any pin with respect to ground .....................................-1.0v to +7.0v maximum operating voltage .......................................... 6.25v dc output current........................................................ 5.0 ma address decoder output buffer do org di cs sk vcc gnd clock generator mode decode logic data register memory array 2048 x 8 or 1024 x 16
3 AT93C86A [preliminary] 3408c?seepr?1/04 note: 1. this parameter is characterized and is not 100% tested. note: 1. v il min and v ih max are reference only and are not tested. pin capacitance (1) applicable over recommended operating range from t a = 25 c, f = 1.0 mhz, v cc = +5.0v (unless otherwise noted). symbol test conditions max units conditions c out output capacitance (do) 5 pf v out = 0v c in input capacitance (cs, sk, di) 5 pf v in = 0v dc characteristics applicable over recommended operating range from: t ai = -40 c to +85 c, v cc = +1.8v to +5.5v, t ae = -40 c to +125 c, v cc = +1.8v to +5.5v (unless otherwise noted). symbol parameter test condition min typ max unit v cc1 supply voltage 1.8 5.5 v v cc2 supply voltage 2.7 5.5 v v cc3 supply voltage 4.5 5.5 v i cc supply current v cc = 5.0v read at 1.0 mhz 0.5 2.0 ma write at 1.0 mhz 0.5 2.0 ma i sb1 standby current v cc = 1.8v cs = 0v 0 0.1 a i sb2 standby current v cc = 2.7v cs = 0v 6.0 10.0 a i sb3 standby current v cc = 5.0v cs = 0v 17 30 a i il input leakage v in = 0v to v cc 0.1 3.0 a i ol output leakage v in = 0v to v cc 0.1 3.0 a v il1 (1) v ih1 (1) input low voltage input high voltage 2.7v v cc 5.5v -0.6 2.0 0.8 v cc + 1 v v il2 (1) v ih2 (1) input low voltage input high voltage 1.8v v cc 2.7v -0.6 v cc x 0.7 v cc x 0.3 v cc + 1 v v ol1 v oh1 output low voltage output high voltage 2.7v v cc 5.5v i ol = 2.1 ma 0.4 v i oh = -0.4 ma 2.4 v v ol2 v oh2 output low voltage output high voltage 1.8v v cc 2.7v i ol = 0.15 ma 0.2 v i oh = -100 a v cc - 0.2 v
4 AT93C86A [preliminary] 3408c?seepr?1/04 note: 1. this parameter is characterized and is not 100% tested. ac characteristics applicable over recommended operating range from t ai = -40c to + 85c, t ae = -40 c to +125 c, v cc = as specified, cl = 1 ttl gate and 100 pf (unless otherwise noted). symbol parameter test condition min typ max units f sk sk clock frequency 4.5v v cc 5.5v 2.7v v cc 5.5v 1.8v v cc 5.5v 0 0 0 2 1 0.25 mhz t skh sk high time 2.7v v cc 5.5v 1.8v v cc 5.5v 250 1000 ns t skl sk low time 2.7v v cc 5.5v 1.8v v cc 5.5v 250 1000 ns t cs minimum cs low time 2.7v v cc 5.5v 1.8v v cc 5.5v 250 1000 ns t css cs setup time relative to sk 2.7v v cc 5.5v 1.8v v cc 5.5v 50 200 ns t dis di setup time relative to sk 2.7v v cc 5.5v 1.8v v cc 5.5v 100 400 ns t csh cs hold time relative to sk 0 ns t dih di hold time relative to sk 2.7v v cc 5.5v 1.8v v cc 5.5v 100 400 ns t pd1 output delay to ?1? ac test 2.7v v cc 5.5v 1.8v v cc 5.5v 250 1000 ns t pd0 output delay to ?0? ac test 2.7v v cc 5.5v 1.8v v cc 5.5v 250 1000 ns t sv cs to status valid ac test 2.7v v cc 5.5v 1.8v v cc 5.5v 250 1000 ns t df cs to do in high impedance ac test cs = v il 2.7v v cc 5.5v 1.8v v cc 5.5v 150 400 ns t wp write cycle time 10 ms 4.5v v cc 5.5v 4 ms endurance (1) 5.0v, 25c, page mode 1m write cycles
5 AT93C86A [preliminary] 3408c?seepr?1/04 functional description the AT93C86A is accessed via a simple and versatile 3-wire serial communication interface. device operation is controlled by seven instructions issued by the host pro- cessor. a valid instruction starts with a rising edge of cs and consists of a start bit (logic ?1?) followed by the appropriate op code and the desired memory address location. read (read): the read (read) instruction contains the address code for the mem- ory location to be read. after the instruction and address are decoded, data from the selected memory location is available at the serial output pin do. output data changes are synchronized with the rising edges of serial clock sk. it should be noted that a dummy bit (logic ?0?) precedes the 8- or 16-bit data output string. the AT93C86A sup- ports sequential read operations. the device will automatically increment the internal address pointer and clock out the next memory location as long as chip select (cs) is held high. in this case, the dummy bit (logic ?0?) will not be clocked out between memory locations, thus allowing for a continuous stream of data to be read. erase/write (ewen): to assure data integrity, the part automatically goes into the erase/write disable (ewds) state when power is first applied. an erase/write enable (ewen) instruction must be executed first before any programming instructions can be carried out. please note that once in the erase/write enable state, programming remains enabled until an erase/write disable (ewds) instruction is executed or v cc power is removed from the part. erase (erase): the erase (erase) instruction programs all bits in the specified memory location to the logical ?1? state. the self-timed erase cycle starts once the erase instruction and address are decoded. the do pin outputs the ready/busy status of the part if cs is brought high after being kept low for a minimum of 250 ns (t cs ). a logic ?1? at pin do indicates that the selected memory location has been erased, and the part is ready for another instruction. write (write): the write (write) instruction contains the 8 or 16 bits of data to be written into the specified memory location. the self-timed programming cycle, t wp , starts after the last bit of data is received at serial data input pin di. the do pin outputs the ready/busy status of the part if cs is brought high after being kept low for a minimum instruction set for the AT93C86A instruction sb op code address data comments x 8 x 16 x 8 x 16 read 1 10 a 10 - a 0 a 9 - a 0 reads data stored in memory, at specified address. ewen 1 00 11xxxxxxxx 11xxxxxxxx write enable must precede all programming modes. erase 1 11 a 10 - a 0 a 9 - a 0 erases memory location a n - a 0 . write 1 01 a 10 - a 0 a 9 - a 0 d 7 - d 0 d 15 - d 0 writes memory location a n - a 0 . eral 1 00 10xxxxxxxx 10xxxxxxxx erases all memory locations. valid only at v cc = 4.5v to 5.5v. wral 1 00 01xxxxxxxx 01xxxxxxxx d 7 - d 0 d 15 - d 0 writes all memory locations. valid when v cc = 4.5v to 5.5v and disable register cleared. ewds 1 00 00xxxxxxxx 00xxxxxxxx disables all programming instructions.
6 AT93C86A [preliminary] 3408c?seepr?1/04 of 250 ns (t cs ). a logic ?0? at do indicates that programming is still in progress. a logic ?1? indicates that the memory location at the specified address has been written with the data pattern contained in the instruction and the part is ready for further instructions. a ready/busy status cannot be obtained if the cs is brought high after the end of the self-timed programming cycle, t wp . erase all (eral): the erase all (eral) instruction programs every bit in the mem- ory array to the logic ?1? state and is primarily used for testing purposes. the do pin outputs the ready/busy status of the part if cs is brought high after being kept low for a minimum of 250 ns (t cs ). the eral instruction is valid only at v cc = 5.0v 10%. write all (wral) : the write all (wral) instruction programs all memory locations with the data patterns specified in the instruction. the do pin outputs the ready/busy status of the part if cs is brought high after being kept low for a minimum of 250 ns (t cs ). the wral instruction is valid only at v cc = 5.0v 10%. erase/write disable (ewds): to protect against accidental data disturb, the erase/write disable (ewds) instruction disables all programming modes and should be executed after all programming operations. the operation of the read instruction is independent of both the ewen and ewds in structions and can be executed at any time.
7 AT93C86A [preliminary] 3408c?seepr?1/04 timing diagrams synchronous data timing note: 1. this is the minimum sk period. organization key for timing diagrams i/o AT93C86A (16k) x 8 x 16 a n a 10 a 9 d n d 7 d 15
8 AT93C86A [preliminary] 3408c?seepr?1/04 read timing ewen timing ewds timing high impedance t cs cs 11 ... 00 1 sk di t cs cs t cs sk di 1 0 000 ...
9 AT93C86A [preliminary] 3408c?seepr?1/04 write timing wral timing (1) note: 1. valid only at v cc = 4.5v to 5.5v. sk cs t cs t wp 11 a n d n 0a0d0 ... ... di do high impedance busy ready cs sk di do high impedance busy ready 1 0 0 1 ... d n t cs t wp ... d0 0
10 AT93C86A [preliminary] 3408c?seepr?1/04 erase timing eral timing (1) note: 1. valid only at v cc = 4.5v to 5.5v. sk 1 1 ... 1 cs di a n t cs t sv t df t wp a n-1 a n-2 a0 check s tat u s standby ready busy do high impedance high impedance sk cs di 1 1 00 0 do high impedance high impedance ready busy check status standby t wp t cs t sv t df
11 AT93C86A [preliminary] 3408c?seepr?1/04 note: for 2.7v devices used in a 4.5v to 5.5v range, please refer to performance values in the ac and dc characteristics tables. AT93C86A ordering information ordering code package operation range AT93C86A-10pi-2.7 AT93C86A-10si-2.7 AT93C86A-10ti-2.7 AT93C86Ay1-10yi-2.7 8p3 8s1 8a2 8y1 industrial (-40 c to 85 c) AT93C86A-10pi-1.8 AT93C86A-10si-1.8 AT93C86A-10ti-1.8 AT93C86Ay1-10yi-1.8 8p3 8s1 8a2 8y1 industrial (-40 c to 85 c) AT93C86A-10su-2.7 AT93C86A-10su-1.8 AT93C86A-10tu-2.7 AT93C86A-10tu-1.8 8s1 8s1 8a2 8a2 lead-free/halogen-free/ industrial temperature (-40 c to 85 c) AT93C86A-10se-2.7 8s1 high grade/extended temperature (-40 c to 125 c) package type 8p3 8-lead, 0.300" wide, plastic dual inline package (pdip) 8s1 8-lead, 0.150" wide, plastic gull wing small outline (jedec soic) 8a2 8-lead, 0.170" wide, thin shrink small outline package (tssop) 8y1 8-lead, 4.90 mm x 3.00 mm body, dual footprint, non-leaded, miniature array package (map) options -2.7 low voltage (2.7v to 5.5v) -1.8 low voltage (1.8v to 5.5v)
12 AT93C86A [preliminary] 3408c?seepr?1/04 packaging information 8p3 ? pdip 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 8p3 , 8-lead, 0.300" wide body, plastic dual in-line package (pdip) 01/09/02 8p3 b d d1 e e1 e l b2 b a2 a 1 n ea c b3 4 plcs top view side view end view common dimensions (unit of measure = inches) symbol min nom max note notes: 1. this drawing is for general information only; refer to jedec drawing ms-001, variation ba for additional information. 2. dimensions a and l are measured with the package seated in jedec seating plane gauge gs-3. 3. d, d1 and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch. 4. e and ea measured with the leads constrained to be perpendicular to datum. 5. pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 (0.25 mm). a 0.210 2 a2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 d 0.355 0.365 0.400 3 d1 0.005 3 e 0.300 0.310 0.325 4 e1 0.240 0.250 0.280 3 e 0.100 bsc ea 0.300 bsc 4 l 0.115 0.130 0.150 2
13 AT93C86A [preliminary] 3408c?seepr?1/04 8s1 ? jedec soic 1150 e. cheyenne mtn. blvd. colorado springs, co 80906 title drawing no. r rev. note: 10/7/03 8s1 , 8-lead (0.150" wide body), plastic gull wing small outline (jedec soic) 8s1 b common dimensions (unit of measure = mm) symbol min nom max note a1 0.10 ? 0.25 these drawings are for general information only. refer to jedec drawing ms-012, variation aa for proper dimensions, tolerances, datums, etc. a 1.35 ? 1.75 b 0.31 ? 0.51 c 0.17 ? 0.25 d 4.80 ? 5.00 e1 3.81 ? 3.99 e 5.79 ? 6.20 e 1.27 bsc l 0.40 ? 1.27 ? 0? ? 8? ? top view end view side view e b d a a1 n e 1 c e1 l
14 AT93C86A [preliminary] 3408c?seepr?1/04 8a2 ? tssop 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 5/30/02 common dimensions (unit of measure = mm) symbol min nom max note d 2.90 3.00 3.10 2, 5 e 6.40 bsc e1 4.30 4.40 4.50 3, 5 a ? ? 1.20 a2 0.80 1.00 1.05 b 0.19 ? 0.30 4 e 0.65 bsc l 0.45 0.60 0.75 l1 1.00 ref 8a2 , 8-lead, 4.4 mm body, plastic thin shrink small outline package (tssop) notes: 1. this drawing is for general information only. refer to jedec drawing mo-153, variation aa, for proper dimensions, toler ances, datums, etc. 2. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. dimension e1 does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. dambar cannot be located on the lower radius of the foot. minimum space between protrusion and adjacent lead is 0.07 mm. 5. dimension d and e1 to be determined at datum plane h. 8a2 b side view end view top view a2 a l l1 d 1 2 3 e1 n b pin 1 indicator this corner e e
15 AT93C86A [preliminary] 3408c?seepr?1/04 8y1 ? map a ? ? 0.90 a1 0.00 ? 0.05 d 4.70 4.90 5.10 e 2.80 3.00 3.20 d1 0.85 1.00 1.15 e1 0.85 1.00 1.15 b 0.25 0.30 0.35 e 0.65 typ l 0.50 0.60 0.70 pin 1 index area d e a a1 b 8 7 6 e 5 l d1 e1 pin 1 index area 1 2 34 a top view end view bottom view side view 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 8y1, 8-lead (4.90 x 3.00 mm body) msop array package (map) y1 c 8y1 2/28/03 common dimensions (unit of measure = mm) symbol min nom max note
printed on recycled paper. 3408c?seepr?1/04 xm disclaimer: atmel corporation makes no warranty for the use of its products, other than those expressly contained in the company?s standar d warranty which is detailed in atmel?s terms and conditions located on the company?s web site. the company assumes no responsibi lity for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time wi thout notice, and does not make any commitment to update the information contained her ein. no licenses to patents or other intellectual property of atmel are granted by the company in connection with the sale of atmel products , expressly or by implication. atmel?s products are not aut horized for use as critical components in life support devices or systems. atmel corporation atmel operations 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 regional headquarters europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel: (41) 26-426-5555 fax: (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel: (33) 2-40-18-18-18 fax: (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel: (33) 4-42-53-60-00 fax: (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906, usa tel: 1(719) 576-3300 fax: 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel: (44) 1355-803-000 fax: (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel: (49) 71-31-67-0 fax: (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906, usa tel: 1(719) 576-3300 fax: 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel: (33) 4-76-58-30-00 fax: (33) 4-76-58-34-80 literature requests www.atmel.com/literature ? atmel corporation 2004 . all rights reserved. atmel ? and combinations thereof, are the registered trademarks of atmel corporation or its subsidiaries. other terms and product names may be the trademarks of others.

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